⇡ Untethered lowRISC tutorial

Simulations and FPGA Demo

This release works with three different simulators and provides an FPGA demo using either a Xilinx Kintex-7 KC705 evaluation kit or a low-end Nexys™4 DDR Artix-7 FPGA Board.

  • Behavioural Simulation (Spike)
    A fast instruction level simulator. The “golden” implementation of Rocket cores.
    Peripheral support from the front-end server (not compatible with the FPGA implemantion).

  • RTL simulation
    RTL-level simulation for the whole lowRISC SoC provided by Verilator.
    Behavioural memory model and simple HTIF for ISA regression test.

  • FPGA demo
    A RISC-V Linux demo on KC705/NEXYS4-DDR.
    Peripherals (KC705): 1GB DDR3 DRAM, UART, SD+FAT32.
    Peripherals (NEXYS4-DDR): 128MB DDR2 DRAM, UART, MicroSD+FAT32.

  • FPGA simulation
    Pre-synthesis FPGA simulation for the whole lowRISC SoC provided by Xilinx ISim (a part of Xilinx Vivado).
    Providing the full peripheral simulation with different configuration options.

  Release Notes