⇡ Tutorial for the v0.6 lowRISC release

Release notes

Release notes

  • Rocket-core (Chisel)

    • Updated to March-2018 vintage together with riscv-tools
    • Rocket repository hierarchy left unmodified for easier updates
    • Compressed instructions and JTAG debugging functional in GDB
    • Clock speed doubled from 25MHz to 50MHz to take advantage of improvements
  • Software environment

    • SD-Card bootloader now uses proper card recognition algorithm
    • SD-cards now run at 10MHz corresponding to Rocket speed boost
    • Ethernet boot loader supports DHCP and is about ten times faster
    • Debian preview release supported with advanced package tool support
    • Linux kernel updated to latest RISCV release
  • lowRISC system-on-chip

    • Accelerated access to all peripherals using 64-bit busses
    • Proper integration of PC-keyboard codes into Linux driver
    • Debian dialog friendly VGA text compatible colour console screen
    • Eight-packet Ethernet receive buffer and Linux driver NAPI-compliant
    • 2K-byte buffer on all UART transmit and receive paths
  • Design environment

    • Updated Vivado synthesis and release to version 2018.1
    • Updated demo images for NEXYS4-DDR FPGA.
    • Minimal Rocket source code changes
    • JTAG debug transport adapted to meet Xilinx hardware constraints
    • Streamlined build more easily meets design constraints.
  • Missing from this release vs the previous

    • Tag memory system not ported to latest Rocket
    • No procedure to build your own userland (Debian download required)
    • Trace debugger not ported to latest Rocket

Previous releases