Today is the second day of the third RISC-V workshop. Again, I’ll be keeping a semi-live blog of talks and announcements throughout the day. See here for notes from the first day.
RISC-V ASIC and FPGA implementations: Richard Herveille Look for freedom of design. Want to free migrate between FPGAs, structured ASICs, standard cell ASICs Want to make it easier to migrate FPGAs to ASICs for advantages in price, performance, power, IP protection.