Many of the lowRISC team (Robert Mullins, Wei Song, and Alex Bradbury) have been in Boston this week for the fourth RISC-V workshop. By any measure, this has been a massive success with over 250 attendees representing 63 companies and 42 Universities. Wei presented our most recent work on integrating trace debug, which you’ll soon be able to read much more about here (it’s worth signing up to our announcement list if you want to be informed of each of our releases).
The lowRISC blog
Begnning on Monday, June 27th, we had a team of four University of Cambridge undergrads begin a 10 week internship working on the lowRISC project at the Computer Laboratory, kindly sponsored by IMC Financial Markets (who are also helping to advise this project). The team will be blogging regularly over the course of the summer - I’ll pass over to them to introduce themselves. After some initial brainstorming, we decided to aim to extend the current lowRISC SoC design to enable video output, with the final goal of playing video smoothly at a resolution of 640x480 on FPGA.
Our friends and collaborators at the Free and Open Source Silicon Foundation have launched the LibreCores design contest. This is a student design contest which aims to recognise and reward contributions to the open source hardware ecosystem. The main evaluation criteria are: Openness. Your work must be published under an established Open Source license. Reusability. How easily can your work be used and modified by someone else? Is it well documented?
The 2016 Google Summer of Code is now underway and we’re delighted to be working with five students, covering a variety of interesting projects. They have all introduced themselves over the past few weeks on our project mailing list. Many thanks to everyone who applied, to the mentors who volunteered, and to Google for sponsoring this programme. If your application was unsuccessful, I hope you’ll try again next year. The projects for lowRISC in the 2016 GSoC are:
We are very grateful to have been selected to take part as a mentoring organisation in the Google Summer of Code for the second year running. As with last year, we’re working with a number of friends from across the wider open source hardware community to act as an umbrella for a range of hardware-related projects. If you are a student who would like to be paid to work on open source during the summer, then take a look at the lowRISC ideas list and apply.
Today is the second day of the third RISC-V workshop. Again, I’ll be keeping a semi-live blog of talks and announcements throughout the day. See here for notes from the first day. RISC-V ASIC and FPGA implementations: Richard Herveille Look for freedom of design. Want to free migrate between FPGAs, structured ASICs, standard cell ASICs Want to make it easier to migrate FPGAs to ASICs for advantages in price, performance, power, IP protection.
The third RISC-V workshop is going on today and tomorrow at the Oracle Conference Center, California. I’ll be keeping a semi-live blog of talks and announcements throughout the day. See here for notes from the second day. Introductions and RISC-V Foundation Overview: Rick O’Connor Save the date, the 4th RISC-V workshop will be July 12th-13th at the MIT CSAIL/Stata Center. In August 2015, articles of incorporation were filed to create a non-profit RISC-V Foundation to govern the ISA.
Over the past several months, we’ve been working to provide a standalone or ‘untethered’ SoC. Cores in the original Rocket chip rely on communicating with a companion processor via the host-target interface (HTIF) to access peripherals and I/O. This release removes this requirement, adding an I/O bus and instantiating FPGA peripherals. The accompanying tutorial, written by Wei Song, describes how to build this code release and explains the underlying structural changes.
Please join us October 9th-11th in Geneva, Switzerland for ORConf 2015. The event is kindly being hosted by CERN at the IdeaSquare. Last year’s ORConf was home to the first public talk on lowRISC and we’re delighted this year it will also be hosting a series of lowRISC and RISC-V discussions, serving as a European lowRISC and RISC-V workshop. ORConf has in recent years grown to cover a range of open source hardware topics beyond the original OpenRISC focus.
It’s the second day of the second RISC-V workshop today in Berkeley, California. I’ll be keeping a semi-live blog of talks and announcements throughout the day. Z-scale. Tiny 32-bit RISC-V Systems: Yunsup Lee Z-Scale is a family of tiny cores, similar in spirit to the ARM Cortex-M family. It integrates with the AHB-Lite interconnect. Contrast to Rocket (in-order cores, 64-bit, 32-bit, dual-issue options), and BOOM (a family of out-of-order cores).