The lowRISC blog

We're hiring! Work on making open source hardware a reality

We are looking for a talented hardware engineer to join the lowRISC team and help make our vision for an open source, secure, and flexible SoC a reality. Apply now! lowRISC C.I.C. is a not-for-profit company that aims to demonstrate, promote and support the use of open-source hardware. The lowRISC project was established in 2014 with the aim of bringing the benefits of open-source to the hardware world. It is working to do this by producing a high quality, secure, open, and flexible System-on-Chip (SoC) platform.

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Building upstream RISC-V GCC+binutils+newlib: the quick and dirty way

There are a number of available options for building a RISC-V GCC toolchain. You might use the build system from the riscv/riscv-tools repository, or investigate toolchain generators such as crosstool-ng. However in the case of riscv-tools, it’s not always clear how this corresponds to the code in the relevant upstream projects. When investigating a potential bug, you often just want to build the latest upstream code with as little fuss as possible.

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lowRISC 0-4 milestone release

The lowRISC 0.4 milestone release is now available. The various changes are best described in our accompanying documentation, but in summary this release: Moves forward our support for tagged memory by re-integrating the tag cache, reducing overhead with a hierarchical scheme. This will significantly reduce caches misses caused by tagged memory accesses where tags are distributed sparsely. Integrates support for specifying and configuring tag propagation and exception behaviour. A PULPino based “minion core” has been integrated, and is used to provide peripherals such as the SD card interface, keyboard, and VGA tex display (when using the Nexys4 DDR FPGA development board).

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Apply now for GSoC 2017

We are very grateful for being selected again to take part as a mentoring organisation in the Google Summer of Code, now for the third year running. If you are a student who would like to be paid to work on open source during the summer, then take a look at the lowRISC ideas list and apply. The deadline for applications is 4pm UTC on April 3rd. We’re always very interested in ideas suggested by students, and encourage you to share them on our discussion list for feedback before making a proposal.

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2017 NetFPGA Design Challenge

As most of you know, the majority of full-time development on lowRISC takes place at the University of Cambridge Computer Laboratory. However, we’re far from the only open source hardware activity at the University. Our colleagues on the NetFPGA project have an open source design challenge that many readers of this blog might be interested in. See the design challenge website, or read below for more details: We are pleased to announce the 2017 NetFPGA Design Challenge!

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lowRISC Q+A

Yesterday, lowRISC triggered a lot of discussion when someone submitted it to Hacker News. The comment thread became something of an impromptu Q+A about our project direction and status. I thought it was worth linking to it here and highlighting the discussion for a wider audience. If you have any additional questions, then feel free to comment on this blog post or else, as always, drop by our mailing list.

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Fifth RISC-V Workshop: Day Two

Today is the second day of the fifth RISC-V workshop. I’ll be keeping a semi-live blog of talks and announcements throughout the day. OpenSoC System Architect: Farzad Fatollahi-Fard Current architectures are wasteful. Only a small fraction of chip area goes to computation. For both GoblinCore and OpenHPC, ended up doing a lot of similar work to achieve only a point design. Why not make a generator to avoid repeating the same steps?

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Fifth RISC-V Workshop: Day One

The fifth RISC-V workshop is going on today and tomorrow at the Google’s Quad Campus in Mountain View. I’ll be keeping a semi-live blog of talks and announcements throughout the day. Introduction: Rick O’Connor and Dom Rizzo This workshop is yet again bigger than the last. 350+ attendees, 107 companies, 29 universities. The next workshop will be May 9th-10 in Shanghai, China. RISC-V at UC San Diego: Michael Taylor Startup software stacks today look a light like an iceberg.

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Generating a Gantt chart from HJSON input

This blog post is a slight departure from the normal topics here. Worry not, we’ll return to discussing Verilog, Chisel, and low-level software work soon. I wrote a quick script to help serve a need (producing a Gantt chart) and thought perhaps others would find it useful. There are a wide range of online services to help produce and maintain Gantt charts, but none quite offered what I was looking for.

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Example Gantt Chart

lowRISC+IMC internship: second update

This is the second update from our team of interns, comprised of four University of Cambridge undergrads. Their work is kindly sponsored by IMC Financial Markets who are also helping to advise this summer project. At the time of our last blog post, we had just finished VGA and were working on implementing the frame buffer. Over the last 2 weeks, we have made significant progress, completing the frame buffer and starting video decode.

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