Several lowRISC team members attended the SiFive Symposium in our home town of Cambridge on May 13th 2019, a lovely sunny day. Imagination Technologies were co-hosting with SiFive, and we heard from both companies. Krste Asanovic, chairman of the board at the RISC-V Foundation, gave a great introduction to RISC-V and progress so far. Naveed Sherwani, CEO of SiFive, talked us through their silicon design platform and future services. We also heard from SecureRF and IAR Systems.
The lowRISC blog
The lowRISC 0.6 milestone release is now available. This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more. See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide. Our next development focus is to add support for dropping in the Ariane RISC-V design (from ETH Zurich) as an alternative to Rocket.
The eighth RISC-V workshop is continuing today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Look back here for the day one live blog. Note that slides from most presentations are now available at riscv.org. Fast interrupts for RISC-V: Krste Asanovic Embedded is a major use for RISC-V. There is a desire for faster interrupt handling with support for nested preempted interrupts.
The eighth RISC-V workshop is going on today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Follow here for the day two live blog. Note that slides from most presentations are now available at riscv.org. Introduction: Rick O’Connor This workshop has 325 attendees representing 101 companies and 25 universties. Largest outside of Silicon Valley. Rick gives the usual overview of the RISC-V Foundation structure.
The lowRISC 0.5 milestone release is now available. The various changes are best described in our accompanying documentation, but the main focus is the integration of open-source Ethernet IP. The tutorial demonstrates how to use Ethernet support to boot with an NFS root, as well as with a rootfs on SD card. Our main development focus currently is migrating to a newer version of the upstream Rocket chip design and reintegrating our changes on top of that, but we felt that the integration of Ethernet support merits a release before that change.
The seventh RISC-V workshop is concluding today at Western Digital in Milpitas. I’ll be keeping a semi-live blog of talks and announcements throughout the day. Celerity: An Open Source 511-core RISC-V Tiered Accelerator Fabric: Michael Taylor Built in only 9 months. Celerity is an accelerator-centric SoC with a tiered accelertor fabric. Implemented in TSMC 16nm FFC. 25mm2 die area, 385M transistors Why 511 RISC-V cores? 5 Linux-capable RV64G Rocket cores, 496-core RV32IM mesh tiled area “manycore”, 10-core RV32IM mesh tiled array (low voltage).
The seventh RISC-V workshop is going on today and tomorrow at Western Digital in Milpitas. I’ll be keeping a semi-live blog of talks and announcements throughout the day. Follow here for the day two live blog. Introduction: Rick O’Connor Workshop is sold out, 498 attendees registered representing 138 companies and 35 universities. There will be 47 sessions squeezed into 12 and 24 minute increments, plus 26 poster / demo sessions.
This year, as part of Google Summer of Code we had the pleasure of working with Nikitas Chronas. Alongside his degree studies, Nikitas had become involved with the Libre Space Foundation and developed a strong interest in the possibility of open source hardware in CubeSats. Fault tolerance of some sort is important for harsh environments, and Nikitas worked to add fault tolerance through the implementation of core lockstep for the PULPino-based minion core subsystem.
A high quality, upstream RISC-V backend for LLVM is perhaps the most frequently requested missing piece of the RISC-V software ecosystem. This blog post provides an update on the rapid progress we’ve been making towards that goal, outlines next steps and upcoming events, and tries to better explain the approach that we’re taking. As always, you can track status here and find the code here. Status I’ve been able to make substantial progress since the last update.
This summer, we were fortunate enough to have Katherine Lim join the lowRISC team at the University of Cambridge Computer Laboratory as an intern. Katherine’s focus was on operating system and software enabled for lowRISC’s tagged memory, building upon our most recent milestone release. As Katherine’s detailed write-up demonstrates, it’s been a very productive summer. The goal of this internship was to take the lowRISC hardware release, and demonstrate kernel support and software support for the hardware tagged memory primitives.