The lowRISC blog

Seventh RISC-V Workshop: Day Two

The seventh RISC-V workshop is concluding today at Western Digital in Milpitas. I’ll be keeping a semi-live blog of talks and announcements throughout the day. Celerity: An Open Source 511-core RISC-V Tiered Accelerator Fabric: Michael Taylor Built in only 9 months. Celerity is an accelerator-centric SoC with a tiered accelertor fabric. Implemented in TSMC 16nm FFC. 25mm2 die area, 385M transistors Why 511 RISC-V cores? 5 Linux-capable RV64G Rocket cores, 496-core RV32IM mesh tiled area “manycore”, 10-core RV32IM mesh tiled array (low voltage).
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Seventh RISC-V Workshop: Day One

The seventh RISC-V workshop is going on today and tomorrow at Western Digital in Milpitas. I’ll be keeping a semi-live blog of talks and announcements throughout the day. Follow here for the day two live blog. Introduction: Rick O’Connor Workshop is sold out, 498 attendees registered representing 138 companies and 35 universities. There will be 47 sessions squeezed into 12 and 24 minute increments, plus 26 poster / demo sessions.
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GSoC 2017 student report: core lockstep for minion cores

This year, as part of Google Summer of Code we had the pleasure of working with Nikitas Chronas. Alongside his degree studies, Nikitas had become involved with the Libre Space Foundation and developed a strong interest in the possibility of open source hardware in CubeSats. Fault tolerance of some sort is important for harsh environments, and Nikitas worked to add fault tolerance through the implementation of core lockstep for the PULPino-based minion core subsystem.
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Moving RISC-V LLVM forwards

A high quality, upstream RISC-V backend for LLVM is perhaps the most frequently requested missing piece of the RISC-V software ecosystem. This blog post provides an update on the rapid progress we’ve been making towards that goal, outlines next steps and upcoming events, and tries to better explain the approach that we’re taking. As always, you can track status here and find the code here. Status I’ve been able to make substantial progress since the last update.
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lowRISC tagged memory OS enablement

This summer, we were fortunate enough to have Katherine Lim join the lowRISC team at the University of Cambridge Computer Laboratory as an intern. Katherine’s focus was on operating system and software enabled for lowRISC’s tagged memory, building upon our most recent milestone release. As Katherine’s detailed write-up demonstrates, it’s been a very productive summer. The goal of this internship was to take the lowRISC hardware release, and demonstrate kernel support and software support for the hardware tagged memory primitives.
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We're hiring! Work on making open source hardware a reality

We are looking for a talented hardware engineer to join the lowRISC team and help make our vision for an open source, secure, and flexible SoC a reality. Apply now! lowRISC C.I.C. is a not-for-profit company that aims to demonstrate, promote and support the use of open-source hardware. The lowRISC project was established in 2014 with the aim of bringing the benefits of open-source to the hardware world. It is working to do this by producing a high quality, secure, open, and flexible System-on-Chip (SoC) platform.
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Building upstream RISC-V GCC+binutils+newlib: the quick and dirty way

There are a number of available options for building a RISC-V GCC toolchain. You might use the build system from the riscv/riscv-tools repository, or investigate toolchain generators such as crosstool-ng. However in the case of riscv-tools, it’s not always clear how this corresponds to the code in the relevant upstream projects. When investigating a potential bug, you often just want to build the latest upstream code with as little fuss as possible.
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lowRISC 0-4 milestone release

The lowRISC 0.4 milestone release is now available. The various changes are best described in our accompanying documentation, but in summary this release: Moves forward our support for tagged memory by re-integrating the tag cache, reducing overhead with a hierarchical scheme. This will significantly reduce caches misses caused by tagged memory accesses where tags are distributed sparsely. Integrates support for specifying and configuring tag propagation and exception behaviour. A PULPino based “minion core” has been integrated, and is used to provide peripherals such as the SD card interface, keyboard, and VGA tex display (when using the Nexys4 DDR FPGA development board).
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Apply now for GSoC 2017

We are very grateful for being selected again to take part as a mentoring organisation in the Google Summer of Code, now for the third year running. If you are a student who would like to be paid to work on open source during the summer, then take a look at the lowRISC ideas list and apply. The deadline for applications is 4pm UTC on April 3rd. We’re always very interested in ideas suggested by students, and encourage you to share them on our discussion list for feedback before making a proposal.
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2017 NetFPGA Design Challenge

As most of you know, the majority of full-time development on lowRISC takes place at the University of Cambridge Computer Laboratory. However, we’re far from the only open source hardware activity at the University. Our colleagues on the NetFPGA project have an open source design challenge that many readers of this blog might be interested in. See the design challenge website, or read below for more details: We are pleased to announce the 2017 NetFPGA Design Challenge!
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