On Monday I proposed promoting the upstream RISC-V LLVM backend from “experimental” to “official” for the LLVM 9.0 release. Responses so far are extremely positive, and we’re working to ensure this is a smooth process. This means that from 9.0, the RISC-V backend will be built by default for LLVM, making it usable out of the box for standard LLVM/Clang builds. As well as being more convenient for end users, this also makes it significantly easier for e.
The lowRISC blog
On June 1st, Sam Elliott followed Laura and Pirmin in becoming lowRISC’s newest employee. A few weeks into his new role, he shares why he joined lowRISC and what he’s been doing since he started. “I joined lowRISC CIC as a Compiler Developer, working on the RISC-V LLVM backend, and so far I’m enjoying working on the team! Prior to lowRISC, I worked as a compilers and programming languages researcher at the University of Washington, where I completed my Masters degree.
Pretty much the whole team is in Zurich this week for the RISC-V Workshop and inaugural Week of Open Source Hardware, with a packed programme that got off to a start today and which runs all the way through to Friday afternoon. This morning lowRISC board member, Professor Luca Benini, gave a RISC-V Workshop keynote entitled, Energy efficient computing from Exascale to MicroWatts: The RISC-V playground. Our friends and close collaborators at PULP Platform are giving a number of talks this week and, we’re pleased to say, so are members of the lowRISC team!
At the beginning of many chips projects, there’s a dream. Could we create a more future-proof chip by embedding an FPGA fabric into it? Could we measure glucose levels more accurately by integrating a small bio lab onto a chip? Could we more reliably recognize kittens in a set of pictures by implementing neural network inference in hardware? In implementation, this dream becomes a piece of hardware, with digital or analog logic, sensors, actuators, and much more.
Pirmin Vogel and Laura James both joined lowRISC on May 1st this year. A few weeks in to their new roles, they each share thoughts on what attracted them to work at lowRISC. Pirmin: “After having traveled around the world for 6 months, I finally started my new position as hardware/software engineer at lowRISC C.I.C. in Cambridge at the beginning of May. At lowRISC, we are working on open-source hardware/software ecosystems with a fully open-sourced, Linux-capable, RISC-V-based SoC being the ultimate goal.
If you haven’t checked it out yet, be sure to take a look at our press release and the corresponding Google blog post. This industry support and growth of our board is a huge step forwards for lowRISC. As Royal Hansen, vice president of Security, Google, said: "Google believes that open source is good for everyone. To further our commitment, we are investing both capital and engineering resources to create a sustainable open source hardware ecosystem.
London, England - lowRISC C.I.C., the open source system on a chip (SoC) organisation, today announced that Prof. Luca Benini (ETH Zurich), Dominic Rizzo (Google) and Ron Minnich (Google) have joined its board of directors. The announcement coincides with a new phase of hiring by lowRISC with the goal of significantly increasing the size of its Cambridge-based engineering team during 2019. lowRISC is a not-for-profit, community-driven organisation working to provide a high quality, security-enabling, open SoC base for derivative designs.
Several lowRISC team members attended the SiFive Symposium in our home town of Cambridge on May 13th 2019, a lovely sunny day. Imagination Technologies were co-hosting with SiFive, and we heard from both companies. Krste Asanovic, chairman of the board at the RISC-V Foundation, gave a great introduction to RISC-V and progress so far. Naveed Sherwani, CEO of SiFive, talked us through their silicon design platform and future services. We also heard from SecureRF and IAR Systems.
The lowRISC 0.6 milestone release is now available. This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more. See the release notes, for full details. We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide. Our next development focus is to add support for dropping in the Ariane RISC-V design (from ETH Zurich) as an alternative to Rocket.
The eighth RISC-V workshop is continuing today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Look back here for the day one live blog. Note that slides from most presentations are now available at riscv.org. Fast interrupts for RISC-V: Krste Asanovic Embedded is a major use for RISC-V. There is a desire for faster interrupt handling with support for nested preempted interrupts.