I’ll be giving a talk in the RISC-V devroom at FOSDEM on Saturday 1st February, in which I’ll describe how we are analysing and improving the performance of the Ibex RISC-V CPU core. I’ll discuss how Verilator is used to simulate Ibex running CoreMark and Embench and how I’ve analysed these simulations to identify major sources of stalls. This is used to inform what improvements should be made. Yosys was used to analyse the impact on area and clock frequency from these changes.
The lowRISC blog
With the recent announcement of OpenTitan, we at lowRISC had many great conversations about the work we do to produce high-quality open source hardware and software. A great place to continue these discussions is the RISC-V Summit in San Jose, CA (Dec 10 - 12, 2019). lowRISC will showcase its work in the conference track and in the exhibit hall. At booth 101, lowRISC will showcase its recent work and our engineers will be around to answer your questions.
Interested in trying out the recently announced OpenTitan? We’ve put together a video that goes through an overview of how the OpenTitan prototype system is put together and how to get up and running with our pre-built release (providing simulator binaries and pre-built FPGA images for the Nexys Video Artix-7 board). It follows the steps from the OpenTitan Quickstart Guide. You can find out more about OpenTitan from our announcement blog and the OpenTitan website.
Today, we are excited to unveil the OpenTitan silicon root of trust (RoT) project, a new effort built using the successful collaborative engineering model created by lowRISC in partnership with Google and other commercial and academic partners. This effort sets a new bar for transparency in trusted silicon, and lowRISC is proud to serve as both steward and not-for-profit engineering contributor to OpenTitan, the world’s first open source silicon RoT.
Organisations aim to make the hardware root more transparent, trustworthy, and secure for everyone. CAMBRIDGE, England–(BUSINESS WIRE)–lowRISC C.I.C., the open source silicon and tools collaborative engineering company, today announced that it has partnered with ETH Zürich, Google, G+D Mobile Security, Nuvoton Technology and Western Digital in support of OpenTitan, an open source hardware root of trust (RoT) reference design and integration guidelines that enable chip producers and platform providers to build transparently implemented, high-quality hardware RoT chips tailored for data center servers and other devices.
Today, we are delighted to announce that Professor Andy Hopper, CBE FRS FIET FREng, has joined the lowRISC Board of Directors as Independent Chair. “I’m delighted to be joining lowRISC CIC,” said Prof. Hopper, speaking today from Cambridge UK, “As digital systems pervade every aspect of our lives trust and transparency become crucial. An open source approach allows for public inspection of the principles and implementations being used. I believe the future of digital systems will be underpinned by not for profit organisations that provide design transparency and enable real innovation.
Greg Chadwick and Tom Roberts recently joined lowRISC’s growing engineering team. They’ve both taken some time to share a little about what they’re doing at lowRISC and what motivated them to join. Greg “It’s an exciting time to join the lowRISC team! Our Ibex core provides a solid foundation and clearly demonstrates the value of open source silicon, which I’m excited to be working on. My work so far has focused on the performance of Ibex; whilst it’s not intended as a high performance core there are various things we can do to improve it without major impact to area or power.
Our microcontroller-class RISC-V processor core Ibex for sure is a solid base with which to start your own project. Over the past months, we have invested a lot of effort in making the design more mature. This includes refactoring the RTL to make the design more understandable and programmer friendly, adding UVM-based verification to the source tree, but also integrating support for the RISC-V compliance suite and enabling publicly visible, open-source powered continuous integration (CI) to keep the design stable.
Ibex, our small RISC-V core, is constantly changing. Roughly 50 percent of the RTL was refactored recently! We added features, tests, and cleaned the code up. We and our collaborators were able to make these changes (mostly) without breaking Ibex because we invested in testing: earlier this year we added UVM-based verification to the tree, and we run these tests after every change. We run static code analysis to catch common programming bugs.
In the past months, we have invested considerable effort in improving our RISC-V core Ibex. This 2-stage, in-order, 32-bit microcontroller-class CPU core was contributed to us by ETH Zürich in December 2018, with activity really ramping up since May. Having been taped out multiple times (as zero-riscy) in a mix of academic and industry projects, it came to us as a relatively mature code base. Despite this, we have continued to invest in improving its design and maintainability.