A fully open-sourced,
Linux-capable,
System-on-a-Chip
Our designs are permissively licensed and developed with collaborators from around the world. We implement the free and open RISC-V ISA.
We are pursuing novel security features such as tagged memory. Unlike proprietary offerings, all aspects of the design can be fully audited.
Hardware needs softening up - through minion cores we enable I/O interfaces and real-time control to be defined in software.
The lowRISC platform aims to be the "Linux of the hardware world", providing a high quality, secure, and open base for derivative designs. We will prove our design with volume silicon manufacture and an accompanying low-cost development board. Our goal is to lower the barrier of entry to producing custom silicon, establishing a vibrant ecosystem around secure and open hardware designs. lowRISC was formed as a not-for-profit community-driven organisation to pursue these aims.
The eighth RISC-V workshop is continuing today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Look back here for the day one live blog. Note that slides from most presentations are now available at riscv.org. Fast interrupts for RISC-V: Krste Asanovic Embedded is a major use for RISC-V. There is a desire for faster interrupt handling with support for nested preempted interrupts. Read More
The eighth RISC-V workshop is going on today in Barcleona. As usual, I’ll be keeping a semi-live blog of talks and announcements throughout the day. Follow here for the day two live blog. Note that slides from most presentations are now available at riscv.org. Introduction: Rick O’Connor This workshop has 325 attendees representing 101 companies and 25 universties. Largest outside of Silicon Valley. Rick gives the usual overview of the RISC-V Foundation structure. Read More
The lowRISC 0.5 milestone release is now available. The various changes are best described in our accompanying documentation, but the main focus is the integration of open-source Ethernet IP. The tutorial demonstrates how to use Ethernet support to boot with an NFS root, as well as with a rootfs on SD card. Our main development focus currently is migrating to a newer version of the upstream Rocket chip design and reintegrating our changes on top of that, but we felt that the integration of Ethernet support merits a release before that change. Read More
The seventh RISC-V workshop is concluding today at Western Digital in Milpitas. I’ll be keeping a semi-live blog of talks and announcements throughout the day. Celerity: An Open Source 511-core RISC-V Tiered Accelerator Fabric: Michael Taylor Built in only 9 months. Celerity is an accelerator-centric SoC with a tiered accelertor fabric. Implemented in TSMC 16nm FFC. 25mm2 die area, 385M transistors Why 511 RISC-V cores? 5 Linux-capable RV64G Rocket cores, 496-core RV32IM mesh tiled area “manycore”, 10-core RV32IM mesh tiled array (low voltage). Read More