lowRISC Minion internals

This lowRISC release introduces Minion cores, allowing I/O tasks to be offloaded from the Rocket. This goal is important because it provides a flexible platform to allow new and unusual devices to be supported. From Chapter 3: extract from Pulpino databook

RISCV core overview from Pulpino databook

The Pulpino as delivered from ETH Zurich is a complete microcontroller, and as such is too large to support our FPGA platform. AXI-compatible busses and peripherals increase the size by 2-3 times. Consequently the decision was taken to only use the core of the previous system, now combined with some key new peripherals:

• Program RAM (64K, tightly coupled)
• Data RAM (64K, tightly coupled)

To prevent problems with speculative pre-fetching, no auto incrementing on peripherals is supported. Therefore an I/O address must be written to before it will yield its first item of data. Although I/O addresses are described as R/W, to save unnecessary hardware, most will not read back what was written.

The built-in UART (only accessible via extra PMOD device), uses a simple protocol. Only the receive side is buffered in this version. Majority voting is implemented to reduce the impact of noise in the environment.

The keyboard FIFO has a 512 word buffer on input, and returns the scan code as its LSB, ASCII representation (British keyboards only), as MSB. The conversion to international alphabets may be done under Linux using its usual facilities. No provision to overwrite the code page is provided in this release, though it would be trivial to implement in hardware. The status output gives the number of keys pending and other FIFO information (see minion_soc.sv). Writing an arbitrary value to this address advances the FIFO to the next character.

The VGA compatible text display is straightforward in operation. No facility for hardware scrolling is offered, the font is a fixed ASCII-font without non-Roman support. No support for overwriting the font is provided though again, it would be trivial in hardware. The output is a fixed 1024x768 at 75Hz. The buffer is a fixed 16K bytes with a 64K memory map, of which only the LSB is used.

The shared memory is 8K bytes, operated as 32-bit quantities on both sides of the interface. No provision for collision detection or interrupts is included in this release. The shared memory appears as an extension to the block memory of the Rocket, consequently it starts at 0x40010000 with the standard Chisel memory map. No detection of the presence of the shared memory is made by the Boot ROM, consequently to detect the presence of the Minion

Minion core connectivity

For details of the SD-protocol, it may be helpful (caution: redacted information) to refer to the SD-association website.

• SD-card association simplified specifications