Tutorial for the v0.4 lowRISC release

By Jonathan Kimmitt, Wei Song and Alex Bradbury (also see acknowledgements below)

Release version 0.4 (06-2017)

Introduction

lowRISC is a not-for-profit organisation whose goal is to produce a fully open source System-on-Chip (SoC) in volume. We are building upon RISC-V processor core implementations from the RISC-V team at UC Berkeley. We will produce a SoC design to populate a low-cost community development board and to act as an ideal starting point for derivative open-source and commercial designs.

In previous tutorials you can learn about trace debugging, the initial tagged memory implementation or how to run the design on an FPGA using our original untethered implementation.

This tutorial adds further functionality towards the final SoC design:

• An optimised tag cache
• The ability to define tag propagation rules and policies for triggering exceptions
• A simple minion core sub-system for accessing the SD-interface, keyboard and VGA-compatible text display

The trace infrastructure is still available but standalone operation with keyboard/display is now possible for the end-user.

The build environment and pre-built images support the same platform as the previous releases, a competitively priced Nexys™4 DDR Artix-7 FPGA Board.

Contents

1. Overview of the Minion system
   • Minion internals

2. Prepare the environment

   • Install FPGA and simulation tools

3. Tagged memory developments

   • Hierarchical tag cache
   • Tag Support

4. Other

   • Debug Walkthrough
   • Running on the FPGA

5. Release notes

   • Version 0.4: minion tag cache lowRISC (6-2017)
   • Version 0.3: trace debugger lowRISC (7-2016)
   • Version 0.2: untethered lowRISC (12-2015)
   • Version 0.1: tagged memory (04-2015)

Work planned / In progress / TO DO

• Interfacing Pulpino (Minion) core to on-chip trace/debug bus.
• Programming Minion dynamically from Rocket under Linux.
• Optimising card transfer speed / Implementing multi-block transfers.
• GDB support under Linux.
• Revised interrupt handling block.
• Ethernet interfacing / booting / Linux support.
• Fully supporting tag instructions in compiler.
• Making tag support thread-safe / context switching safe.
• More security demos.
• Userland software running on the Rocket.
• Offloading SD-card acceleration and Video scrolling to Minion.
• Run-control debug for Rocket.

Acknowledgements

• Stefan Wallentowitz and Philipp Wagner provided the trace debug system
• Furkan Turan provided the zedboard patches
• Philipp Jantscher did the initial tagged memory port to debug-v0.3

Other useful sources of information

• Open SoC Debug (Overview slides)