Build your own bitstream and images

Generate the bitstream

FPGA demo with Ethernet (default bootloader)

cd $TOP/fpga/board/nexys4_ddr
make cleanall
make bitstream

The generated bitstream is located at lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit. This will take some time (20-60 minutes depending on your computer).

Program the bootloader on FPGA

Next, turn on the FPGA board and connect the USB cable. Now you download the bitstream to the quad-SPI on the FPGA board:

make cfgmem
make program-cfgmem

At this point, you should check the MODE jumper is in QSPI mode and then press the PROG button.

Boot Linux remotely on FPGA

make etherboot

FPGA demo with Ethernet (alternative boot programs)

cd $TOP/fpga/board/nexys4_ddr
make cleanall
make target (where target is eth, selftest, dram, hello etc.)

The generated bitstream is located at lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.new.bit. This will take some time (20-60 minutes depending on your computer).

Program the alternative boot programs on FPGA

Next, turn on the FPGA board and connect the USB cable. Now you download the bitstream to the quad-SPI on the FPGA board:

make cfgmem-updated
make program-cfgmem-updated

Build Linux and early stage root filing system

make verilog (automatically included if make bitstream is done above)

$TOP/riscv-tools/make_root.sh

If everything runs OK, you should have a boot.bin file.

Please note that the Berkeley bootloader used by the Linux kernel relies on a header file (dev_map.h) generated by the Rocket chip (automatically generated by the Chisel compilation process). Normally FPGA bitstream should be generated before building a kernel image. If you like to generate a kernel image without a bitstream, run the following to produce the header file:

cd $TOP/fpga/board/nexys4_ddr
CONFIG=Nexys4Config make verilog

Build riscv-poky

cd $TOP/ricv-poky
source oe-init-build-env
bitbake core-image-riscv

This scripting system generates a huge set of downloads, all of which are built from source. This can take half or day on a fast connection and consumes 26GBytes or so of disk space. For these reasons, unless there is a need to modify the installed packages, the user who wishes to quick start might prefer to download the prebuild image. The source code is similar to the standard riscv-poky but with some customisation of device names and configuration.

Useful Makefile targets

make project

Generate a Vivado project.

make verilog

Run Chisel compiler and generate the Verilog files for Rocket chip.

make vivado

Open the Vivado GUI using the current project.

make bitstream

Generate the default bitstream according to the CONFIG in Makefile and the program loaded in src/boot.mem. The default bitstream is generated at lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit

make <hello|dram|sdcard|boot|jump|trace|flash>

Generate bitstreams for bare-metal tests:

For each bare-metal test <test>, the executable is generated to examples/<test>.riscv. It is also converted into a hex file and copied to src/boot.mem, which then changes the default program for make bitstream and make simulation. The updated bitstream is generated at lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.new.bit

make <program|program-updated>

Download a bitstream to FPGA. Use program for lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit and program-updated for lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.new.bit

make <cfgmem|cfgmem-updated>

Convert a bitstream to the format suitable for quad-SPI flash on the FPGA board. Use cfgmem for lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit and cfgmem-updated for lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.new.bit

make <program-cfgmem|program-cfgmem-updated>

Download a bitstream to quad-SPI flash on the FPGA board. Use program-cfgmem for lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.bit and program-cfgmem-updated for lowrisc-chip-imp/lowrisc-chip-imp.runs/impl_1/chip_top.new.bit

make <clean|cleanall>

make clean will remove all generated code without removing the Vivado project files. To remove all files including the Vivado project, use make cleanall.