lowRISC with a trace debugger
Release version 0.3, 07-2016
In this code release we present a first prototype of the lowRISC debug infrastructure. It extends the
untetheredlowRISC system with the means to control the system, load programs and trace the software execution. The tutorial outlines the debug system and the future directions we are planning. It demonstrates debugging with the RTL simulation and on the Nexys4 DDR FPGA board.
Release version 0.2, 12-2015
A code release providing a standalone lowRISC by
untetheringthe Rocket chip. Cores in the original Rocket chip relies on a companion processor to access I/O devices. This release repalce this companion core with actual FPGA peripherals. A tutorial explains how to use this code release and explains the underlying structural changes.
lowRISC with tagged memory
Release version 0.1, 04-2015
A code release builds on the Rocket RISC-V implementation to offer support for tagged memory (see the release blog post). We’ve put together an extensive tutorial on how to use this code release as well as documenting many of the changes made.
Our first memo describes our plans for tagged memory and minion cores in lowRISC.
Over the summer of 2016 we hosted a group of interns, kindly sponsored by IMC Financial Markets who worked on adding custom acceleraors for video decoding to the lowRISC platform. This work resulted in the creation of several documents:
- A detailed report on what was produced over the summer, what went well and what didn’t, as well as a description of the accelerators.
- A tutorial on adding new stream processors to the video accelerator infrastructure developed over the summer.
- A tutorial on extending lowRISC with new devices.
- A guide describing how to recreate the video decode demo.