lowRISC is producing fully open hardware systems. From the processor core to the development board, our goal is to create a completely open computing eco-system.

Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit RISC-V instruction set architecture. Volume silicon manufacture is planned as is a low-cost development board. There are more details on our plans in these slides from a recent talk

lowRISC is a not-for-profit organisation working closely with the University of Cambridge and the open-source community.

To keep track of the project, follow @lowRISC or join our announcements list by entering your email below:

If you want to get in touch, please email info@lowrisc.org

Recent milestones

May 2015: This summer we have six students working on Summer of Code projects. The coding period is from the end of May to the end of August.

Apr 2015: We have shared our first lowRISC preview release, demonstrating support for tagged memory as described in our memo. This FPGA-compatible code release is accompanied by an extensive tutorial.

Mar 2015: We are excited to announce we are taking part in the Google Summer of Code 2015. See our ideas list for a wide range of projects in different languages and covering pretty much every level of the hardware/software stack.

Dec 2014: We have now released a document describing our plans for tagged memory and minion cores in the lowRISC SoC.

The Team (founders)

  • Robert Mullins - Computer Laboratory, University of Cambridge, co-founder of Raspberry Pi
  • Gavin Ferris - Dreamworks, Radioscape (co-founder), Aspect Capital (former CIO)
  • Alex Bradbury - Computer Laboratory, University of Cambridge and Raspberry Pi

Technical Advisory Board


Summer of Code students for lowRISC

lowRISC was fortunate enough to be chosen as a mentoring organisation in this year’s Google Summer of Code. The Google Summer of Code program funds students to work on open source projects over the summer. We had 52 applications across the range of project ideas we’ve been advertising. As you can see from the range of project ideas, lowRISC is taking part as an umbrella organisation, working with a number of our friends in the wider open source software and hardware community. We were allocated three slots from Google, and given the volume of high quality applications making the selection was tremendously difficult. We have actually been able to fund an additional three applicants from other sources, but even then there were many promising projects we couldn’t support. We are extremely grateful to all the students who put so much time and effort in to their proposals, and to everyone who volunteered to mentor. The six ‘summer of code’ projects for lowRISC are:

  • An online Verilog IDE based on YosysJS. Baptiste Duprat mentored by Clifford Wolf

    • Baptiste will be working with an Emscripten-compiled version of the Yosys logic synthesis tool, building an online Verilog IDE on top of it which would be particularly suitable for training and teaching materials. A big chunk of the proposed work is related to visualisation of the generated logic. Improving the accessibility of hardware design is essential for growing the potential contributor base to open source hardware projects like lowRISC, and this is just the start of our efforts in that space.
  • Porting seL4 to RISC-V. Hesham ALMatary mentored by Stefan Wallentowitz

    • seL4 is a formally verified microkernel, which currently has ports for x86 and ARM. Hesham will be performing a complete port to RISC-V/lowRISC. Security and microkernels are of great interest to many in the community. It’s also a good opportunity to expand RISC-V platform support and to put the recently released RISC-V Privileged Architecture Specification through its paces. Hesham previously performed a port of RTEMS to OpenRISC.
  • Porting jor1k to RISC-V. Prannoy Pilligundla mentored by Sebastian Macke

    • jor1k is by far the fastest Javascript-based full system simulator. It also features a network device, filesystem support, and a framebuffer. Prannoy will be adding support for RISC-V and look at supporting some of the features we offer on lowRISC such as minion cores or tagged memory. This will be great not only as a demo, but also have practical uses in tutorial or educational material.
  • TCP offload to minion cores using rump kernels. Sebastian Wicki mentored by Justin Cormack

    • The intention here is to get a rump kernel (essentially a libified NetBSD) running bare-metal on a simple RISC-V system and evaluate exposing the TCP/IP stack for use by other cores. e.g. a TCP/IP offload engine running on a minion core. TCP offload is a good starting point, but of course the same concept could be applied elsewhere. For example, running a USB mass storage driver (and filesystem implementation) on a minion core and providing a simple high-level interface to the application cores.
  • Extend Tavor to support directed generation of assembly test cases. Yoann Blein mentored by Markus Zimmermann

    • Tavor is a sophisticated fuzzing tool implemented in Go. Yoann will be extending it to more readily support specifying instruction set features and generating a fuzzing suite targeting an ISA such as RISC-V. Yoann has some really interesting ideas on how to go about this, so I’m really interested in seeing where this on ends up.
  • Implement a Wishbone to TileLink bridge and extend TileLink documentation. Thomas Repetti mentored by Wei Song

    • Wishbone is the interconnect of choice for most existing open source IP cores, including most devices on opencores.org. The Berkeley Rocket RISC-V implementation uses their own ‘TileLink’ protocol (we provide a brief overview. By providing a reusable bridge, this project will allow the easy reuse of opencores devices and leverage the many man-years of effort that has already gone in to them.

The first 3 of the above projects are part of Google Summer of Code and the bottom 3 directly funded, operating over roughly the same timeline. We’re also going to be having two local students interning with us here at the University of Cambridge Computer Lab starting towards the end of June, so it’s going to be a busy and productive summer. It bears repeating just how much we appreciate the support of everyone involved so far - Google through their Summer of Code initiative, the students, and those who’ve offered to act as mentors. We’re very excited about these projects, so please join us in welcoming the students involved to our community. If you have any questions, suggestions, or guidance please do leave them in the comments.

Alex Bradbury

lowRISC tagged memory preview release

We’re pleased to announce the first lowRISC preview release, demonstrating support for tagged memory as described in our memo. Our ambition with lowRISC is to provide an open-source System-on-Chip platform for others to build on, along with low-cost development boards featuring a reference implementation. Although there’s more work to be done on the tagged memory implementation, now seemed a good time to document what we’ve done in order for the wider community to take a look. Please see our full tutorial which describes in some detail the changes we’ve made to the Berkeley Rocket core, as well as how you can build and try it out for yourself (either in simulation, or on an FPGA). We’ve gone to some effort to produce this documentation, both to document our work, and to share our experiences building upon the Berkeley RISC-V code releases in the hopes they’ll be useful to other groups.

The initial motivation for tagged memory was to prevent control-flow hijacking attacks, though there are a range of other potential uses including fine-grained memory synchronisation, garbage collection, and debug tools.
Please note that the instructions used to manipulate tagged memory in this release (ltag and stag) are only temporary and chosen simply because they require minimal changes to the core pipeline. Future work will include exploring better ISA support, collecting performance numbers across a range of tagged memory uses and tuning the tag cache. We are also working on developing an ‘untethered’ version of the SoC with the necessary peripherals integrated for standalone operation.

If you’ve visited lowrisc.org before, you’ll have noticed we’ve changed a few things around. Keep an eye on this blog (and its RSS feed) to keep an eye on developments - we expect to be updating at least every couple of weeks. We’re very grateful to the RISC-V team at Berkeley for all their support and guidance. A large portion of the credit for this initial code release goes to Wei Song, who’s been working tirelessly on the HDL implementation.