lowRISC is producing fully open hardware systems. From the processor core to the development board, our goal is to create a completely open computing eco-system.
Our open-source SoC (System-on-a-Chip) designs will be based on the 64-bit RISC-V instruction set architecture. Volume silicon manufacture is planned as is a low-cost development board. There are more details on our plans in these slides from a recent talk
lowRISC is a not-for-profit organisation working closely with the University of Cambridge and the open-source community.
Dec 2014: We have now released a document describing our plans for tagged memory and minion cores in the lowRISC SoC.
To keep track of the project, follow @lowRISC or join our announcements list by entering your email below:
- Robert Mullins - Computer Laboratory, University of Cambridge, co-founder of Raspberry Pi
- Gavin Ferris - Dreamworks, Radioscape (co-founder), Aspect Capital (former CIO)
- Alex Bradbury - Computer Laboratory, University of Cambridge and Raspberry Pi
Technical Advisory Board
- Krste Asanovic (UC Berkeley)
- Julius Baxter (OpenRISC)
- Bunnie Huang (Hacker)
- Dominic Rizzo (Google ATAP)
- Michael Taylor (UCSD)
Do you have a discussion list?
Are you hiring?
The closing date for the first round of applications has recently closed. We will hopefully have new positions available soon, please feel free to send CVs to email@example.com .
Are contract or remote working arrangements on offer?
We are not currently looking for contract or remote workers, but may in the future. If we do, we'll advertise via this website and the announcement list.
What are the goals of the project?
- To create a fully open SoC and low-cost development board and to support the open-source hardware community. This will involve volume silicon manufacture.
- To explore and promote novel hardware security features
- To make it simple for existing companies and especially semiconductor startups to create derivative designs, e.g. by sharing scripts, tools, source and our experience
- To create a benchmark design to aid academic research
When can I buy a lowRISC SoC?
As with most tech projects, the most accurate answer is "When it's ready". However, it's useful to consider some of the main milestones:
- Release of an initial FPGA version: we expect to do this in the next 6 months, and then further development will be fully open to the community.
- Production of a test chip: we expect to tape out a test chip towards the end of 2015.
- Tape out of production silicon: this is likely to happen, at the earliest, a year after the first test chip (in 2016).
Why RISC-V and not OpenRISC/SPARCv8/MIPS/...?
We considered two aspects when surveying the potentially instruction set architectures (ISAs), firstly the features of the ISA itself and secondly the existence of high performance designs. RISC-V is a 64-bit, contemporary clean-sheet design. Implementations exist in an open-source HDL (Chisel) and multiple high performance test chips have been produced, at 45 and 28nm. When performing this survey, the requirement that the ISA be freely implementable rules out most ISAs currently used by the industry. We did consider using older versions of commercial ISAs (i.e. versions where all relevant patents would have expired), but this raises the issue of how to go about bringing them up to date. To avoid legal uncertainty, we would have to make arbitrarily different choices to the original vendor, which means compatibility would be lost.
What features and peripherals will the SoC have?
We'll distribute draft specifications as soon as is reasonable. The plan is to share as much as possible as early as possible.
How will your designs be licensed?
A permissive open-source license.
How is this different to Raspberry Pi?
Our goals and focus are quite different. The Raspberry Pi exists to improve computer science education worldwide. A fully open-source SoC is not necessary to reach this goal, or even a pragmatic way of achieving it given the timescales involved. While it is an ultimate goal to support all the features of a modern commercial SoC, it will require a number of iterations of the design to achieve this. For example, early versions of our SoC will not include a GPU.
What is your relationship to Raspberry Pi?
We know the team well but this is a completely independent project. Robert co-founded Raspberry Pi, while Alex is a contributor since the very early days of the project.
What level of performance will it have?
To run Linux "well". The clock rate achieved will depend on the technology node and particular process selected. As a rough guide we would expect ~500-1GHz at 40nm and ~1.0-1.5GHz at 28nm.
Is volume fabrication feasible?
Yes. There are a number of routes open to us. Early production runs are likely to be done in batches of ~25 wafers. This would yield around 100-200K good chips per batch. We expect to produce packaged chips for less than $10 each.
How can I contribute?
In the coming months we will be launching mailing lists, a Wiki and of course a source code repository to publicly coordinate development of the project. This will include both hardware and software work. We hope to have interesting, evidence-backed debates about implementation options out in the open.