Our designs are permissively licensed and developed with collaborators from around the world. We implement the free and open RISC-V ISA.
We are pursuing novel security features such as tagged memory. Unlike proprietary offerings, all aspects of the design can be fully audited.
Hardware needs softening up - through minion cores we enable I/O interfaces and real-time control to be defined in software.
The lowRISC platform aims to be the "Linux of the hardware world", providing a high quality, secure, and open base for derivative designs. We will prove our design with volume silicon manufacture and an accompanying low-cost development board. Our goal is to lower the barrier of entry to producing custom silicon, establishing a vibrant ecosystem around secure and open hardware designs. lowRISC was formed as a not-for-profit community-driven organisation to pursue these aims.
We are very grateful for being selected again to take part as a mentoring organisation in the Google Summer of Code, now for the third year running. If you are a student who would like to be paid to work on open source during the summer, then take a look at the lowRISC ideas list and apply. The deadline for applications is 4pm UTC on April 3rd. We’re always very interested in ideas suggested by students, and encourage you to share them on our discussion list for feedback before making a proposal. Read More
As most of you know, the majority of full-time development on lowRISC takes place at the University of Cambridge Computer Laboratory. However, we’re far from the only open source hardware activity at the University. Our colleagues on the NetFPGA project have an open source design challenge that many readers of this blog might be interested in. See the design challenge website, or read below for more details: We are pleased to announce the 2017 NetFPGA Design Challenge! Read More
Yesterday, lowRISC triggered a lot of discussion when someone submitted it to Hacker News. The comment thread became something of an impromptu Q+A about our project direction and status. I thought it was worth linking to it here and highlighting the discussion for a wider audience. If you have any additional questions, then feel free to comment on this blog post or else, as always, drop by our mailing list. Read More
Today is the second day of the fifth RISC-V workshop. I’ll be keeping a semi-live blog of talks and announcements throughout the day. OpenSoC System Architect: Farzad Fatollahi-Fard Current architectures are wasteful. Only a small fraction of chip area goes to computation. For both GoblinCore and OpenHPC, ended up doing a lot of similar work to achieve only a point design. Why not make a generator to avoid repeating the same steps? Read More